1. Field of the Invention
The present invention relates to a method for manufacturing a chip-scale package, and more particularly, to a method for manufacturing a chip-scale package ("CSP") using a lead frame strip having a plurality of lead frames, for facilitating mass production of CSPs.
2. Description of the Related Art
The continued trend toward miniaturization of electronic and electrical systems requires a reduction in the overall size of the semiconductor device packages that are employed therein. Packages having good reliability, multi-function capability, as well as a small size are thus required.
A so-called CSP ("chip scale package" or "chip size package") can satisfy the miniaturization and multi-function requirements, since it is as small as a bare chip and can be mounted using surface mount technologies.
However, the CSP suffers some drawbacks in that sophisticated and expensive production equipment is required. Also, the CSP is produced in individual units, rather than in strip form. Both of these drawbacks greatly increase the production cost of the device.
FIG. 1 is a schematic cross-sectional view of a conventional chip-scale package manufactured by Tessera Corp. The CSP 100 has bonding pads 12 on the bottom surface of the chip 10 that are electrically connected to respective ones of the corresponding flexible patterns 20. Insulating polyimide film 40 is bonded to the bottom surface of flexible patterns 20. The polyimide film 40 has via holes coated with a conductive material on their inner wall, through which the flexible patterns 20 are electrically connected to solder bumps 60. An elastomer 30 is interposed between the flexible patterns 20 and the parts of the bottom surface of the chip 10 where no bonding pads are formed. The chip 10 is immobilized by a handling ring 50.
This type of package is basically a micro-BGA (ball grid array) package using a flip chip interconnection technology. This structure is advantageous in that it can be subjected to various tests such as burn-in tests, as well as allowing for high density mounting and efficient heat dissipation. However, this type of package is expensive to produce and also requires a production line that is set up to perform many independent processes, which is not conducive to mass production.
FIG. 2 is a cut-away perspective view of another example of conventional chip-scale package developed by Mitsubishi Corp. The CSP 200 has bonding pads 112 formed on the central part of the upper surface of chip 110 that are electrically connected to respective ones of the corresponding solder bumps 160 via circuit patterns 120 on the upper surface of the chip 110. The chip 110, circuit patterns 120 and electrical interconnections 112 are encapsulated with a molding compound 150 to provide protection from the external environment. The solder bumps 160 are exposed through the surface of the molding compound 150.
In addition to the advantages of the CSP device shown in FIG. 1, the device in FIG. 2 has the additional advantage of flexibility in that the bonding pads can be located at many positions. However, one drawback is that the relatively large size of the solder bumps make it difficult to satisfy high pin device requirements. Also, the manufacturing process is complex and expensive since the circuit patterns are formed during the wafer fabricating process. Furthermore, the devices must be produced individually, rather than achieving the economies of mass production.